1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device and a method of manufacturing the same improved such that the device isolation suitable for miniaturization is performed.
2. Description of the Background Art
Conventionally, a LOCOS (Local Oxidation of Silicon) method is used as an element isolating method in an MOS IC using a silicon as a semiconductor.
FIG. 5 is a sectional view of a conventional semiconductor device in which elements are isolated by the LOCOS method. Referring to FIG. 5, a P well 2 formed on the main surface of an n type semiconductor substrate 1. The P well 2 is isolated from another element (not shown) by a field oxide film 3. A gate electrode 5 is provided on the main surface of the P well 2 through a gate insulating film 4. Source and drain layers 6 are formed on the main surface of the P well 2 (except for a portion beneath the gate electrode 5). A conventional semiconductor device in which the elements are isolated by the LOCOS method is structured as described above. According to the element isolation by this LOCOS method, an isolation area can be relatively small, but on the other hand, there was a disadvantage that there was a limit of the reduction in an isolated width because of a bird's beak 3a at the end portions of the field oxide film 3. In addition, as an element is miniaturized, it becomes necessary to make a high impurity concentration of a silicon substrate in the element isolating region. In this case, as a transistor channel width is decreased, a threshold voltage Vth of an MOS transistor is increased, which is known as a narrow channel effect. Therefore, the LOCOS method is not satisfactory because the element has been increasingly miniaturized recently.
As an improvement on the LOCOS method, a field plate method has been proposed. FIG. 6 is a sectional view of the conventional semiconductor device in which elements are isolated by the field plate method disclosed in Japanese Patent Laying-Open Gazette No. 66444/1985. Referring to FIG. 6, a field oxide film 3 is formed on an element isolating region of the semiconductor substrate 1 by the LOCOS method. A field plate 7 is formed on the field oxide film 3. An MOSFET comprising source and drain layers 6, a gate insulating film 4 and a gate electrode 5 is formed on an active region isolated by the field oxide film 3. According to this conventional example, since the potential on the field plate 7 on the field oxide film is the same as that of the semiconductor substrate 1, a parasitic MOS transistor is always off, so that a leak current is prevented from being generated. However, in this field plate method, it is necessary to align the field oxide film 3 with the field plate 7 and there was a difficulty in this alignment. In addition, there was a disadvantage that there was a limit of decrease in an isolated width because of the bird's beak 3a at the end portions of the field oxide film 3 in this method.
In order to improve these disadvantages, a field shield method has been proposed by which a field oxide film is formed thin and a field shield is formed thereon to isolate elements.
FIG. 7 is a sectional view of a semiconductor device in which elements are isolated by the field shield method disclosed in Japanese Patent Laying-Open Gazette No. 206874/1987. Referring to FIG. 7, a P well 2 is formed on the main surface of an n type semiconductor substrate 1. An MOSFET comprising source and drain layers 6, a gate electrode 5 formed on the surface of the P well 2 through a second gate insulating film 4 in the P well 2. A field shield 9 comprising polysilicon is formed on an element isolating region of the semiconductor substrate 1 through the first gate insulating film 8. The principle of the element isolation by this field shield method is as follows. That is, in an MOS structure comprising the field shield 9, the first gate insulating film 8 and the P well 2, a p.sup.+ layer 10 is formed on the surface of the semiconductor substrate by applying a negative voltage to the field shield 9 to electrically isolate elements by the p.sup.+ layer 10.
The element isolation by the conventional field shield method is structured as described above. When the above-described field shield method is applied to the submicron isolation, it is necessary to introduce something serving as a channel cut beneath the field shield 9 after the formation of the field shield 9 in order to avoid the parasitic MOS effect. However, it was difficult to implement isolation without the introduction of something serving as this channel cut. In addition, there was another disadvantage that the MOS threshold voltage Vth of the MOSFET transistor is increased together with the decrease in the channel width of the transistor by the narrow channel effect if something serving as the channel cut is introduced beneath the field shield after the formation of the field shield 9. Therefore, it was difficult to implement the submicron isolation by the above-described field shield method in the present condition.